Low voltage high performance semiconductor devices and methods

ABSTRACT

A method for adjusting V t  while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

FIELD OF THE INVENTION

[0001] This invention relates to low voltage, high performancesemiconductor devices, such as MOS transistors for dynamic random accessmemory (DRAM) cells and logic applications, and to methods forfabricating such devices. More specifically, the present inventionrelates to methods for adjusting threshold voltage for high speedsemiconductor transistor devices without the need for any additionalmasks.

BACKGROUND OF THE INVENTION

[0002] MOS processes typically begin with a lightly-doped P-type orN-type silicon substrate. For the sake of simplicity, the conventionalMOS process will be described using P-type silicon as the startingmaterial. If N-type silicon were used, the process steps would bevirtually identical, with the exception that the dopant types would bereversed.

[0003] Silicon, the most commonly used semiconductor material can bemade conductive by doping (introducing an impurity into the siliconcrystal structure) with either an element such as boron, which has oneless valence electron than silicon, or with elements such as phosphorusor arsenic, which have one more valence electron than silicon.

[0004] In the case of boron doping, electron “holes” become the chargecarriers and the doped silicon is referred to as positive or P-typesilicon. In the case of phosphorus or arsenic doping, the additionalelectrons become the charge carriers and the doped silicon is referredto as negative or N-type silicon. If dopants of opposite typeconductivity are used, counter-doping will result, and the conductivitytype of the most abundant impurity will prevail.

[0005] The P-well regions are oxidized using a conventional LOCOS (LOCalOxidation of Silicon) step to create a silicon oxide layer. During theLOCOS process, the pad oxide serves as a stress relief layer.Alternatively, oxide growth and oxide deposition steps over silicontrench can replace the LOCOS step.

[0006] The channel regions of the future N-channel transistors are thenexposed to a high-energy boron punch-through implant. This implantincreases both source-to-drain breakdown voltage and the thresholdvoltage (V_(t)), thus avoiding short-channel effects. The successfuloperation of MOS circuits is very dependent on the ability to controlthreshold voltage (V_(t)). The threshold voltage (V_(t)) of a transistoris the voltage necessary for turning the transistor on or off. Accuratecontrol of V_(t) is made possible by ion implantation. V_(t) adjustmentimplantation into the channel usually takes place through a sacrificialgate oxide, before the growth of a gate oxide and deposition of thepolysilicon for the gate electrodes.

[0007] In conventional MOS processes, after V_(t) adjustment a layer ofpolysilicon is then deposited on top of the gate oxide usingconventional means (e.g., chemical vapor deposition). The poly layer isthen doped with phosphorus, and coated with a layer of tungsten silicideby various possible techniques (e.g., chemical vapor deposition,sputtering, or evaporation). A further photomask then patterns thesilicide-coated polysilicon layer to form the transistor gates.

[0008] The N-channel source and drain regions are next exposed to arelatively low-dosage phosphorus implant which creates lightly-dopeddrain (LDD) N-regions. Following the stripping of this mask, a layer ofsilicon dioxide or nitride is deposited on the wafer. An anisotropicetch and a subsequent optional isotropic etch of the silicon dioxidelayer leave oxide spacers on the sides of each transistor gate.

[0009] A photomask then exposes the source and drain regions to arelatively high-dosage phosphorus or arsenic implant, which createsheavily-doped N+ regions. A photomask is then used to define contactswhich will pass through an isolation oxide, e.g., BPSG glass, layer tothe poly structures or active area conductive regions below. Adeposition of an aluminum metal layer follows. Another photomask is thenused to pattern the aluminum layer for circuit interconnects. Using ablanket deposition process, the circuitry is then covered with one ormore passivation layers. An additional photomask then defines bondingpad openings, which will expose bonding pad regions on the aluminumlayer below. This completes a conventional MOS process.

[0010] The business of producing semiconductor devices is a verycompetitive, high-volume business. Process efficiency andmanufacturability, as well as product quality, reliability, andperformance (speed) are key factors that determine success or failure.Each new generation of devices is expected to be faster and more compactthan the generation it replaces.

[0011] In low voltage design, low threshold voltage (V_(t)) is essentialsince the current drive is proportional to (V_(G)−V_(t)) where V_(G) isthe gate voltage. Because very precise quantities of impurity can beintroduced using ion implantation, it is possible to maintain closecontrol of V_(t). A problem arises, however, in connection with ionimplantation for punch through prevention in such devices. Implanting aboron dopant, for example, for punch through prevention increases V_(t),and creates a barrier layer at the junction between the N+ type sourceand drain regions and the underlying P-type substrate, thus increasingparasitic capacitance at this junction. This parasitic capacitancereduces the speed of the device.

[0012] A method is needed for adjusting V_(t), while minimizingparasitic capacitance and without introducing any additionalphotomasking steps.

SUMMARY OF THE INVENTION

[0013] The invention provides a low voltage, high speed semiconductortransistor device having low V_(t) and reduced parasitic capacitance.Reduction in parasitic capacitance, and hence increase in speed, isachieved by shadowing out an angled punch through prevention ion implantbetween a transistor gate and adjacent structures to shadow out aportion of the implant. The resulting, minimally diffused implantresults in a relatively lighter dose toward the edge of the transistorgate than the central regions of the source and drain, thus reducingV_(t) and parasitic junction capacitance in those regions. The low V_(t)and reduced parasitic capacitance devices may be produced together withhigher V_(t) devices elsewhere on the chip without any additionalmasking steps to make the low V_(t) devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a sectional view of a semiconductor wafer fragment atone processing step in accordance with the invention.

[0015]FIG. 2 is a view of the FIG. 1 wafer taken at a step subsequent tothat shown by FIG. 1. FIG. 2 shows the formation of actual gate, anddummy gate (or poly runners over field oxide), structures at apredetermined height (H) and spacing (S). FIG. 2 also shows formation ofa lightly doped drain LDD between such structures.

[0016]FIG. 3 is a view of the FIG. 1 wafer taken at a step subsequent tothat shown by FIG. 2, and shows self-aligned formation of source anddrain regions.

[0017]FIG. 4 is a view of the FIG. 1 wafer taken at a step subsequent tothat shown by FIG. 3, and shows spacering of actual gate, and dummygates (or poly runners over field oxide), and angled implant for punchthrough prevention. FIG. 4 also shows a gradation in the P-N junctionregion of the active area as a result of the shadow effects caused bythe angled implant and the structures at distances H and S.

[0018]FIG. 5 is a view of the FIG. 1 wafer taken at a step subsequent tothat shown by FIG. 4, and shows one method of contact formation tosource and drain regions.

[0019]FIG. 6 is a view of the FIG. 1 wafer taken at a step subsequent tothat shown by FIG. 4, and shows an alternative method of contactformation to source and drain regions.

[0020]FIG. 7 is an alternative embodiment showing a view of the FIG. 1wafer taken at a step subsequent to FIG. 1, and shows formation of alightly doped drain and angled implant for punch through prevention,both prior to spacering of actual gate and dummy gates (or polyrunners).

[0021]FIG. 8 depicts examples of various circuits containing both lowV_(t) devices and high or normal V_(t) devices according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0022] The figures are not meant to be actual cross-sectional views ofany particular portion of a real semiconductor device, but are merelyconvenient tools employed to more fully depict the process aspect of theinvention at various stages of manufacture.

[0023] The term “substrate” herein shall be understood to mean one ormore semiconductive layers or structures which include active oroperable portions of semiconductor devices.

[0024] An exemplary construction of a fabrication process for a lowvoltage semiconductor transistor device according to one embodiment ofthe present invention is described below. It is to be understood,however, that this process is only one example of many possibleprocesses. For example, the angled V_(t) adjustment implant is shadowedout by a transistor gate and a dummy gate in the following process. Aseries of actual-gates, interconnect structures and actual, or dummy,gates, poly runners or other structures could also be used. As anotherexample, additional implant steps may be employed to optimize impurityprofiles in particular regions, and the sequence of implant steps couldbe changed so long as the punch through prevention implant is carriedout after one or more structures are deposited and subsequentlypatterned with sufficient height and sufficiently small spacing toshadow out the angled implant.

[0025] Referring to FIG. 1, a first pad oxide layer 11 is grown onlightly-doped P-type silicon substrate 12. Silicon substrate 12 isisolated into active region 10 by field oxide regions 13. LOCalOxidation of Silicon (LOCOS), shallow trench isolation (STI) or otherfield isolation techniques known in the art are used to provide oxideregions 13 for patterning silicon substrate 12 into active region 10. Asan example of an STI process, a silicon nitride layer (not shown) can bedeposited on a silicon dioxide layer which is previously thermally grownon silicon substrate 12. The silicon nitride layer is patterned suchthat the silicon nitride layer remains only on active region 10. Asilicon trench is then etched to a depth of typically 2-3 times thejunction depth of the devices,,i.e., about 0.20 to 0.40 micron. Thesilicon sidewalls and trench bottom are then oxidized to a thickness ofabout 100-200 angstroms to serve as a liner. Then a high conformal oxidedeposition is performed to fill both the trench and the wide open fieldarea. The oxide is subsequently planarized by chemical mechanicalpolishing (CMP) to the level of the nitride underneath, to expose thenitride. The STI process is preferred in the method of the presentinvention due to the greater degree of flatness or planarity which itprovides.

[0026] Referring to FIG. 2, after isolation of active region 10, gatestructure 18 which includes polycrystalline silicon 14, an overlyingsilicide layer 15 such as tungsten silicide or other highly conductivematerials, and an insulating cap 16, preferably SiO₂ or Si₃N₄, areformed using conventional semiconductor gate processing techniques. InFIG. 2 gate structure 18 is the actual transistor gate above activeregion 10. Gate structures 26 above field oxide regions 13 are dummygates or poly runners. Dummy gates 26 are preferably formed at the sametime and using the same steps as used for formation of gate structure18. The height (H) of deposited polycrystalline silicon 14, silicide 15and cap 16 (with optional spacer material) is the desired final heightof gate structure 18 and dummy gate structures 26 for the semiconductordevice. This height (H) is preferably greater than conventional gatestructures so as to facilitate the shadow effects of the angled implantto adjust V_(t) in subsequent steps. Patterned photoresist is used as anetch mask in forming gate structure 18 and dummy gates 26. In FIG. 2,the patterned photoresist has been removed.

[0027] Referring still to FIG. 2, after formation of gate structure 18,a conventional self-aligning lightly doped (LDD) implant 20 is performedto form lightly doped regions 17 as shown. For N-channel semiconductordevices, the LDD implant 20 is an N-type dopant. For a P-channel device,the LDD implant is a P-type dopant.

[0028] The implant energy of the LDD implant 20 is sufficient topenetrate the exposed portion of active region 10 but not sufficient topenetrate active region 10 under gate structure 18. Thus, gate structure18 serves as an implant mask to block the LDD implant 20. In LDD region17, the implant energy of the LDD implant 20 controls the peakconcentration depth. Lightly doped drain region 17 reduces the electricfield of the semiconductor device by grading the doping level of activeregion 10. This doping level gradation is discussed below in connectionwith FIG. 4.

[0029] Although not shown in FIG. 2, a patterned photoresist mayoptionally be used to prevent self-aligning LDD implant 20 frompenetrating other active regions which do not require the implant. Thephotoresist covered active regions include those used for semiconductordevices with a channel of a different conductivity type compared to thatof the semiconductor device of gate structure 18 or to block certainspecies from being implanted into the memory array. The patternedphotoresist is removed after performing LDD implant 20.

[0030] Referring to FIG. 3, LDD implant 20 is followed by a chemicalvapor deposition (CVD) of oxide or nitride to create a spacer oxidelayer 19 having a thickness in the range of 200 to 2000 angstroms,depending upon device geometry. Spacer oxide layer 19 is then etchedwith an anisotropic etch, to form a set of sidewall spacers 19 fortransistor gates 18. Spacer oxide layer 19 coats the sides of transistorgate 18, so that when the wafer is subsequently subjected to an N-typeimplant, N-type source/drain regions are created for N-channel devices,and these N-type source/drain regions are offset from the verticalboundaries of LDD implant regions 17 by the vertical segments of spaceroxide layer 19 on the edge of the N-channel transistor gates 18.

[0031] Referring still to FIG. 3, a high-dosage arsenic or phosphorusimplant then creates self-aligned heavily doped N-type source/drainregions 23 for N-channel devices. The high-dosage implant isself-aligned to the edges of the N-channel transistor gate 18.

[0032]FIG. 3 depicts self-aligning implant 22 performed after formationof gate structure 18 and oxide spacer 19. The self-alignment of implant22 is particularly preferred for small geometry devices. Implant 22introduces dopant into active region 10 to overlap LDD region 17 to formsource and drain regions 23. To form semiconductor devices with anN-channel, dopant 22 is a dopant having an N-type conductivity such asphosphorous, arsenic, or the like. Dopant 22 is, of course, of adifferent conductivity type than that of the substrate to form asemiconductor device with a channel of the different conductivity type.

[0033] The implant energy of dopant 22 during implant 22 is sufficientto penetrate active region 10 in source and drain region 23, i.e., theimplant energy is preferably low to form shallow junctions. Gatestructure 18 serves as an implant mask to block implant 22. In sourceand drain region 23, the implant energy of dopant 22 controls the depthof the peak concentration of implant 22. An additional implant can beused to optimize the dopant profile of source and drain region 23.

[0034] As depicted in FIG. 3, a portion of source and drain region 23will exist underneath a portion of spacer 19, in that a portion of LDDregion 17 exists underneath a portion of gate structure 18 since the LDDimplant is performed prior to the formation of spacer 19. Thus, aportion of LDD region 17 is converted into source and drain region 23 byimplant 22. LDD region 17 and source and drain region 23 are of the sameconductivity type. As shown in FIG. 3, spacer 19 is used to blockimplant 22 from completely overlapping LDD region 17. Since the dose ofimplant 22 is higher than the dose of the LDD implant, the dopingconcentration of source and drain region 23 is higher than the dopingconcentration of LDD region 17, and the doping concentration of LDDregion 17 does not significantly affect the doping concentration ofsource and drain region 23. Source and drain region 23 has a higherN-type doping concentration, and LDD region 17 has a lower N-type dopingconcentration. A portion of the original LDD region exists to provide agraded doping concentration to reduce the electric field in activeregion 10 to increase the breakdown voltage of the semiconductor device.

[0035] Referring to FIG. 4, after formation of source and drain regions23, the wafer is subjected to angled low-dosage boron implant 21, usinga mask which is usually the same mask as the N+ source/drain mask, toserve as an N-channel punch through voltage enhancement, creating punchthrough implant regions 24 that extend to the edges of transistor gate18 and dummy gate 26. Punch through prevention implant 21 introducesdopant into active region 10, and may increase V_(t) of small devices byas much as several hundred mVs. To form a semiconductor device with anN-channel, the implanted dopant 21 is a dopant having a P-typeconductivity such as boron. Dopant 21 is of a different conductivitytype to prevent punch through in a channel of the different conductivitytype. A P-type dopant is implanted into an N-channel device to preventpunch through. Similarly, an N-type dopant, such as phosphorous, can beimplanted into an N-channel device to adjust the threshold voltage in anegative direction.

[0036] In conventional silicon processing, the threshold voltageadjustment implant is performed prior to formation of gate structure 18and spacer 19. In the process of the present invention, the gatestructure serves as a mask for the angled implant 21, and the implant 22(FIG. 3) which creates the source and drain regions.

[0037] Although implant 21 is a different conductivity type than implant22, the implant dose of implant 22 is approximately 3 orders ofmagnitude higher than the implant dose of implant 21. Therefore,although P-type punch through prevention implant 21 is implanted intoN-type source and drain region 23, the lower concentration of P-typedopant 21 does not significantly affect the higher concentration ofN-type dopant 22. A similar effect is observed if implant 21 uses anN-type dopant.

[0038] Implant 21 is performed at a boron implant dose of approximately2×10¹¹ to 8×10¹³ atoms/cm² and an implant energy of approximately 10 to100 keV, preferably about 40 to 60 keV.

[0039] Punch through prevention implants typically create a higherconcentration P-type region below the N-type source and drain regionsthan created in the channel region under gate structures, and thusincrease source and drain junction capacitances. This increase in P-Njunction capacitance degrades speed and power performance. In order toovercome this problem, the method of the present invention uses anangled implant 21 in which the relatively tall (H) gate structurespartially shadow out implant 21. When the implant angle φ is between 5°and 45° as shown in FIG. 4, and the gate or other structures aresufficiently high so that the implant angle is preferably slightlygreater than Arc tangent S/H, where S is the horizontal distance betweengate structure 18 and dummy gates 26 (or other structures), only a thinlayer of boron is created in region 24 below the source and drainregions. However, a somewhat higher dose of boron is implanted in outerregions 25 of the source and drain. Only about one-half of the usualdose is implanted in the central region 24 of the source and drainbecause, due to four rotational implants (one for each 90° rotation ofthe substrate), only two directions are implanted. Due to the fourrotational implants, and depending upon the angle φ and distances (H)and (S), three directions can be implanted into outer regions 25. As aresult of the angled implant 21 and shadow effects, the V_(t) is about200-300 mv lower than would be achieved without the shadow effects and,more importantly, the junction capacitance between the source tosubstrate and drain to substrate is reduced, thus increasing devicespeed. Various different angles, and distances (H) and (S) can beemployed in the method of the invention, so long as at least a portionof the implant is shadowed out resulting in gradation of the implanteddopant concentration.

[0040] Implants 21 and 22 are subsequently annealed to activateimplanted dopants 21 and 22, respectively. The high temperature annealor rapid thermal anneal is preferably of a short time duration toprevent dopant diffusion associated with long diffusion anneals and toeliminate problems associated with dopant diffusion.

[0041] Referring now to FIG. 5, conventional processing technology maybe used to complete the circuitry. Preferably all structures are firstcovered by an oxide isolation layer (not shown), which may be doped withphosphorus, boron or both. In FIG. 5, a photomask (not shown) has beenused to define contacts 28 from metal layer 31 through oxide isolationlayer through which connection to poly plug structures 27 and activearea conductive regions below can be made. FIG. 5 shows buried digitline 29 as one preferred embodiment. For example, referring to FIG. 6,an alternative embodiment is shown which utilizes a self-aligned contactetch for tungsten metal contacts 30. Various processing steps known inthe art can be used to complete the circuitry.

[0042] Additional variations of the present invention includeinterchanging the processing order of source and drain implant 22 andpunch through prevention implant 21. In addition, the implant 21 can beformed together with the LDD implant step before spacer formation. FIG.7 illustrates process steps in this alternative embodiment. Furthermore,the semiconductor manufacturing process embodied in the presentinvention to produce MOS semiconductor transistor devices can also beused to produce MESFET, CMOS, and BiCMOS devices.

[0043] One advantage of the present invention is that low V_(t) devicesmay be made on a chip containing normal or high V_(t) devices withoutthe need for any additional masking step. The invention thus lendsitself well to various applications in which low voltage devices areminority devices on a given chip. These applications, include, forexample, NMOS pass transistor devices (FIG. 8A), pre-charge circuits(FIG. 8B) and output drivers (FIG. 8C). With reference to FIG. 8A,V_(TL) represents a low threshold voltage device, which preferably has alow V_(t) so as to maximize output level at VO, due to the V_(t) drop.Voltage V₁ after a pass transistor is preferably high to have good driveon the device Ml. The smaller the V_(t), the lower the drop. Withreference to FIG. 8B, the node 1 voltage of the pre-charge circuitV_(PR) is preferably high so that it can properly drive the subsequentdriver. Accordingly, a V_(TL) device is provided between V_(PR) and node1. FIG. 8C shows another circuit in which the output is a V_(t) dropaway from the input voltage V_(CC). Given the disclosure and teachingsof the present invention, these and various other circuits can now beconveniently made with both low V_(t) and high V_(t) devices withoutadditional or complex processing steps.

[0044] Although several embodiments of the improved process have beendescribed herein, it will be apparent to one skilled in the art thatchanges and modifications may be made thereto without departing from thespirit and the scope of the invention as claimed. The same process flowcould be used to create P-channel and N-channel devices on alightly-doped N-type substrate (arsenic or phosphorus-doped siliconhaving a conductivity opposite to that of the lightly-doped P-typesubstrate used to begin the process described in detail heretofore). Insuch a case, a P-well, rather than an N-well would be created in thesubstrate, and so forth. Moreover, the process approach explained hereinwas in the context of a single actual gate, but any structure may beutilized to shadow out the punch through prevention implant. Preferably,such structures are of sufficient height (H) and spacing (S) such thatthe implant angle is greater than or equal to arc tangent S/H. Thestructures may include, for example, an actual gate for one device andan adjacent actual gate of another device, or an actual gate for onedevice and an interconnect structure such as a poly runner for that sameor another device.

[0045] Accordingly, the above description and accompanying drawings areonly illustrative of preferred embodiments which can achieve and providethe objects, features and advantages of the present invention. It is notintended that the invention be limited to the embodiments shown anddescribed in detail herein. The invention is only limited by the spiritand scope of the following claims.

We claim:
 1. A method of manufacturing a semiconductor device of a firstconductivity type fabricated on a semiconductor substrate, the methodcomprising: providing a semiconductor substrate; isolating an activeregion on the semiconductor substrate; forming a gate structure on theactive region; forming a second structure on the semiconductorsubstrate, said second structure having a height (H) and being formed ata distance (S) from said gate structure; implanting a dopant of a secondconductivity type into the active region, wherein said dopant isimplanted at an angle with respect to the surface of said substrate, andsaid second structure causes a shadow effect upon implantation of saidsecond dopant such that the amount of dopant implanted increasesapproaching said gate structure from a point in the active region aboutone-half the distance (S) from said gate structure.
 2. The method ofclaim 1 wherein said angle is at least about Arc tangent S/H.
 3. Themethod of claim 1 further comprising implanting a dopant of the firstconductivity type into the active region, wherein said dopant isimplanted with a first implant energy and with a first implant dose,wherein the gate structure prevents said dopant from penetrating theactive region under the gate structure during implanting of said dopant.4. The method of claim 3 wherein said step of implanting a dopant of thefirst conductivity type is performed prior to implanting said dopant ofa second conductivity type.
 5. The method of claim 1 further includingimplanting the dopant of a second conductivity with an implant energy ofabout 10 keV to 100 keV.
 6. The method of claim 5 further includingimplanting the dopant of a second conductivity with an implant dose ofabout 2×10¹¹ atoms/cm² to 8×10¹³ atoms/cm².
 7. The method of claim 6further including implanting boron for the dopant of a secondconductivity.
 8. The method of claim 1 wherein said gate structure doesnot include side spacers.
 9. The method of claim 1 further comprisingthe step of forming side spacers on said gate structure and wherein saidstep of implanting a dopant of said second conductivity type isperformed prior to forming said side spacers.
 10. The method of claim 1wherein forming the second structure includes providing a dummy gatestructure.
 11. The method of claim 1 further including forming a spaceron the active region and in contact with the gate structure.
 12. Themethod of claim 9 wherein said dopant of a first conductivity and saiddopant of a second conductivity are implanted after formation of saidspacer.
 13. The method according to claim 10, further includingimplanting a third dopant into the active region, wherein the thirddopant is of the first conductivity and is implanted before formation ofsaid spacer.
 14. A method of manufacturing a semiconductor device, themethod comprising: providing a substrate; isolating an active region onthe substrate; forming a gate structure of a first height on the activeregion; forming a second structure of a second height at a firstdistance from the gate structure; implanting a dopant into the activeregion, wherein the dopant is implanted at an angle greater than orequal to Arc tangent of the product of the second height and the inverseof the first distance.
 15. The method of claim 14 further includingimplanting the dopant with an implant energy of about 10 keV to 100 keV.16. The method of claim 15 further including implanting the dopant withan implant dose of about 2×10¹¹ atoms/cm² to 8×10¹³ atoms/cm².
 17. Themethod of claim 14 further including implanting boron for the dopant.18. The method of claim 14 further including implanting phosphorous forthe dopant.
 19. The method of claim 14 further including implanting thedopant into the active region wherein the first height of the gatestructure is similar to the second height of the second structure duringimplanting of the dopant.
 20. The method of claim 14 wherein the dopantis implanted at an angle of from 5° to 45° with respect to saidsubstrate.
 21. A method of manufacturing a semiconductor device with achannel of a first conductivity type, the method comprising: providing asilicon substrate; isolating an active region on the silicon substrate;forming a gate structure having a height on the active region; forming asecond structure having height (H) and being separated from the gatestructure by a first distance (S); implanting a first dopant of thefirst conductivity type into the active region, wherein the gatestructure blocks the first dopant from penetrating the active regionunder the gate structure during implanting of the first dopant;implanting a second dopant of a second conductivity type into the activeregion, wherein the second dopant is implanted at an angle such that therelationship between the height of the second structure and the distancebetween the second structure and the gate structure blocks directimplant of the second dopant into at least a portion of the activeregion; and annealing the first dopant and the second dopant.
 22. Themethod of claim 21 wherein the relationship between H and S is such thatthe implant angle for the second dopant is at least about the arctangent of S/H.
 23. A method of manufacturing a semiconductor device,the method comprising: providing a semiconductor substrate; isolating anactive region in the semiconductor substrate; forming a gate structureover a portion of the active region; forming a second structure spacedapart a horizontal distance from said gate structure; implanting a firstdopant into the active region, the gate structure preventing the firstdopant from penetrating the active region under the gate structureduring implanting of the first dopant; implanting a second dopant intothe active region, the second dopant penetrating the active region,wherein the second dopant is implanted at an angle directly into a firstportion of the active region but blocked by the gate and secondstructures such that the second dopant diffuses into a second portion ofthe active region; and implanting a third dopant into the active region,wherein the third dopant does not penetrate the active region under thegate structure.
 24. A semiconductor device, comprising: a semiconductorsubstrate having an active region; a gate structure on said activeregion, said gate structure having a first height; at least one secondstructure spaced apart from said gate structure by a first distance, andsaid at least one second structure having a second height; source anddrain regions adjacent to said gate structure; a punch throughprevention implant dopant below at least one of said source and drainregions, wherein said dopant forms a barrier between said source ordrain and the underlying substrate and said barrier is graded such thatthe dopant concentration increases toward said gate structure, anddecreases away from said gate structure toward the central region ofsaid source or drain.
 25. A semiconductor device according to claim 24wherein said at least one second structure comprises a dummy gate.
 26. Asemiconductor device according to claim 24 wherein said at least onesecond structure comprises at least one poly runner.
 27. A semiconductordevice according to claim 24 wherein said source or drain region isbetween said gate structure and said second structure.
 28. Asemiconductor device according to claim 27 comprising at least twosecond structures, wherein one is on either side of the gate structureand said source and drain are between said gate and second structures.29. A semiconductor device according to claim 24 wherein said first andsecond heights are substantially the same.
 30. A semiconductor deviceaccording to claim 24 wherein said barrier thickness increases towardssaid at least one second structure and decreases away from said secondstructure toward the central region of said source or drain.